1. Field of the Invention
The present invention relates to an on-chip bypass capacitor and methods of manufacturing the same.
2. Description of the Related Art
FIG. 1 illustrates a simplified diagram of a power supply network 10. The power supply network 10 may have parasitic elements, including resistive, on-chip, parasitic elements and inductive, off-chip, parasitic elements. Further, a current drawn across-these elements may induce a noise voltage represented by:Ri+Ldi/dt
In the power supply network 10 of FIG. 1, a 10 watt chip may draw 4 amps at 2.5 volts (DC current), but may have a peak current of 10-20 amps.
A difference between the peak and average current may be supplied by a local on-chip bypass capacitor or a decoupling capacitor to filter noise. The different between the peak current and the average current is illustrated in FIG. 2.
Conventional processes may form an on-chip bypass capacitor during the same fabrication process as is used to form corresponding cell capacitors. The voltage across a cell capacitor of a memory cell may be represented by(VINT−VSS)/2.
However, the voltage difference across an on-chip bypass capacitor may be represented by VINT/VSS, which may cause the oxide of the on-chip capacitor to break down more rapidly than an oxide of the cell capacitor.